The present invention relates to semiconductor devices and methods of fabricating the same, and more particularly, to single transistor floating body dynamic random access memory (DRAM) cells having a recess channel transistor structure and methods of fabricating the same.
A dynamic random access memory (DRAM) is one kind of volatile memory device. A DRAM has a plurality of DRAM cells storing digital data, i.e., “0”s and “1”s. A structure using one capacitor, one transistor, and interconnections to implement the DRAM cell is widely employed. However, as electronic products using semiconductor devices are being made increasingly thin, light-weight, and compact, it has generally become necessary to highly integrate DRAMs. That is, as many DRAM cells as possible are formed within a limited area. However, techniques for highly integrating the DRAMs are faced with several limits.
For example, the capacitor generally has a top electrode, a bottom electrode, and a capacitor dielectric layer. The top and bottom electrodes have a mutually overlapping region in which the capacitor dielectric layer is formed. The capacitance of the capacitor is typically directly proportional to the size of the overlapping region and inversely proportional to the thickness of the capacitor dielectric layer. Reducing the size of the capacitor as much as possible is conducive to achieving high integration of the DRAM. However, reduction of the size of the capacitor generally causes a decrease in capacitance. Reducing the thickness of the capacitor dielectric layer to increase the capacitance may result in leakage current. In addition, the overlapping region may be extended to increase capacitance, but this technique generally increases the difficulty of certain processes, such as a process for increasing an aspect ratio.
To overcome such limitations, a single transistor floating body DRAM cell has been researched. The single transistor floating body DRAM cell generally has a single transistor having a floating body region and omits the capacitor. Thus, the single transistor floating body DRAM cell has a structural advantage over the DRAM cell in terms of high integration as it need not include a cell capacitor.
FIG. 1 is a cross-sectional view of a conventional single transistor floating body DRAM cell. As shown in FIG. 1, the conventional single transistor floating body DRAM cell has a buried oxide layer (BOX) 12 formed on a semiconductor substrate 10. A floating body 13, a source region 16, and a drain region 17 are formed on the BOX 12. A gate dielectric layer 14 and a gate electrode 15 are sequentially stacked on the floating body 13. The source region 16 is connected to a ground GND, the drain region 17 is connected to a bit line BL and the gate electrode 15 is connected to a word line WL.
As shown in FIG. 1, the floating body 13 is electrically isolated by the BOX 12, the gate dielectric layer 14, the source region 16, and the drain region 17. The single transistor floating body DRAM cell stores and reads data using a floating body effect.
An operation of writing (storing) data to the single transistor floating body DRAM cell will now be described. The source region 16 is grounded, a word line program voltage greater than a threshold voltage is applied to the gate electrode 15 and a bit line program voltage is applied to the drain region 17. The write operation generates holes in the floating body 13 near the drain region 17, which are accumulated within the floating body 13 and change the threshold voltage.
An operation of reading data from the single transistor floating body DRAM cell will now be described. The source region 16 is grounded, a word line read voltage lower than the word line program voltage is applied to the gate electrode 15 and a bit line read voltage is applied to the drain region 17. In this case, an amount of current flowing between the source region 16 and the drain region 17 changes in response to whether the holes are present. That is, the amount of current flowing between the source region 16 and the drain region 17 is sensed to read data stored in the single transistor floating body DRAM cell.
In addition, the threshold voltage changes according to the number of accumulated holes. That is, the current flowing between the source region 16 and the drain region 17 changes in response to the number of accumulated holes.
However, the gate electrode 15 generally must be reduced in size in order to highly integrate the conventional single transistor floating body DRAM cell. Reduction of the size of the gate electrode 15 is accompanied by reduction of a channel length formed within the floating body 13. The reduction of the channel length typically causes a short channel effect, which may include drain-induced barrier lowering (DIBL) and sub-threshold swing.
Reduction of the channel length causes a barrier between the source region 16 and the drain region 17 to be reduced. That is, the threshold voltage changes in response to a voltage difference between the source region 16 and the drain region 17. This phenomenon is referred to as DIBL. The DIBL typically makes it difficult to control a drain current by means of the threshold voltage.
In addition, an inversion layer may be formed within the floating body 13 in the case of a voltage lower than the threshold voltage, i.e., a sub-threshold voltage. Accordingly, a small amount of current may flow between the source region 16 and the drain region 17 even when the sub-threshold voltage is applied to the gate electrode 15. That is, a sub-threshold swing may occur. As a result, the reduction of the channel length may make it difficult to turn off the transistor.
The DIBL and the sub-threshold swing may degrade a sensing margin of the single transistor floating body DRAM cell. That is, the short channel effect may make it difficult to store and read data in the single transistor floating body DRAM cell.
A single transistor floating body DRAM cell is described in Japanese Patent Laid-Open Publication No. 2003-31693 entitled “Semiconductor Memory Device” to Osawa Takashi. Another single transistor floating body DRAM cell is described in U.S. Pat. No. 6,661,042 entitled “One-transistor Floating Body DRAM Cell in Bulk CMOS Process with Electrically Isolated Charge Storage Region” to Hsu.